We’re condemned to suffer uninformed masses on this. Zen 5 mobile is on N4p at 143transistors/um2, the M4max is on N3E at 213transistors/um2. That’s a gigantic advantage in power savings and logic per mm2 of die. Granted, I don’t think the chiplet design will ever reach ARM levels of power gating but that’s a price I’m willing to pay to keep legacy compatibility and expandable RAM and storage. That IO die will always be problematic unless they integrate it in the SOC but I’d prefer if they don’t. (Integration also has power saving advantages, just look at Intel’s latest mobile foray)
Not to mention, Apple is able to afford the larger die size per chip since they do vertical integration and don’t have to worry about the cost of each chip in the way that Intel and AMD has to when they sell to device manufacturers.
We’re condemned to suffer uninformed masses on this. Zen 5 mobile is on N4p at 143transistors/um2, the M4max is on N3E at 213transistors/um2. That’s a gigantic advantage in power savings and logic per mm2 of die. Granted, I don’t think the chiplet design will ever reach ARM levels of power gating but that’s a price I’m willing to pay to keep legacy compatibility and expandable RAM and storage. That IO die will always be problematic unless they integrate it in the SOC but I’d prefer if they don’t. (Integration also has power saving advantages, just look at Intel’s latest mobile foray)
Not to mention, Apple is able to afford the larger die size per chip since they do vertical integration and don’t have to worry about the cost of each chip in the way that Intel and AMD has to when they sell to device manufacturers.