Currently studying CS and some other stuff. Best known for previously being top 50 (OCE) in LoL, expert RoN modder, and creator of RoN:EE’s community patch (CBP).

(header photo by Brian Maffitt)

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Joined 1 year ago
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Cake day: June 17th, 2023

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  • Rise of Nations (originally released back in 2003) had/has some interesting ideas to reduce some of the busywork:

    • Worker units will automatically try to gather/build nearby after a short (configurable) delay if they’re not doing anything.
    • Cities (the main worker-producing structure) has a rally point option that’s essentially “all nearby empty resource gathering”, so you can queue a dozen workers and they’ll distribute themselves as they’re created.
    • Production buildings can be set to loop over their current queue, letting you build continually without intervention as long as you maintain enough resources each time the queue “restocks”.
    • Units that engage in combat without being given an explicit target will try (with modest success) to aim for nearby units which they counter.

    For the most part, none of the implemented options are strictly better than micromanaging them yourself:

    • You will always spend less time idling workers if you micromanage them yourself.
    • The auto-rally-point doesn’t always prioritize the resources that you would if you did it yourself.
    • Queueing additional units is slightly less resource-efficient than only building one thing at a time.
    • Total DPS is higher if you manually micro effectively.

    But the options are there when you need them, which I think is a a nice design. It doesn’t completely remove best-in-class players being rewarded for their speed as a player, but does raise the “speed floor”, allowing slower players to get more bang for their buck APM-wise, and compete a bit more on the strategy/tactics side of the game instead.








  • Submitted for good faith discussion: Substack shouldn’t decide what we read. The reason it caught my attention is that it’s co-signed by Edward Snowden and Richard Dawkins, who evidently both have blogs there I never knew about.

    I’m not sure how many of the people who decide to comment on these stories actually read up about them first, but I did, such as by actually reading the Atlantic article linked. I would personally feel very uncomfortable about voluntarily sharing a space with someone who unironically writes a post called “Vaccines Are Jew Witchcraftery”. However, the Atlantic article also notes:

    Experts on extremist communication, such Whitney Phillips, the University of Oregon journalism professor, caution that simply banning hate groups from a platform—even if sometimes necessary from a business standpoint—can end up redounding to the extremists’ benefit by making them seem like victims of an overweening censorship regime. “It feeds into this narrative of liberal censorship of conservatives,” Phillips told me, “even if the views in question are really extreme.”

    Structurally this is where a comment would usually have a conclusion to reinforce a position, but I don’t personally know what I support doing here.







  • Typically no, the top two PCIE x16 slots are normally directly to the CPU, though when both are plugged in they will drop down to both being x8 connectivity.

    Any PCIE x4 or X1 are off the chipset, as well as some IO, and any third or fourth x16 slots.

    I think the relevant part of my original comment might’ve been misunderstood – I’ll edit to clarify that but I’m already aware that the 16 “GPU-assigned” lanes are coming directly from the CPU (including when doing 2x8, if the board is designed in this way – the GPU-assigned lanes aren’t what I’m getting at here).

    So yes, motherboards typically do implement more IO connectivity than can be used simultaneously, though they will try to avoid disabling USB ports or dropping their speed since regular customers will not understand why.

    This doesn’t really address what I was getting at though. The OP’s point was basically “the reason there isn’t more USB is because there’s not enough bandwidth - here are the numbers”. The missing bandwidth they’re mentioning is correct, but the reality is that we already design boards with more ports than bandwidth - hence why it doesn’t seem like a great answer despite being a helpful addition to the discussion.


  • Isn’t this glossing over that (when allocating 16 PCIe lanes to a GPU as per your example), most of the remaining I/O connectivity comes from the chipset, not directly from the CPU itself?

    There’ll still be bandwidth limitations, of course, as you’ll only be able to max out the bandwidth of the link (which in this case is 4x PCIe 4.0 lanes), but this implies that it’s not only okay but normal to implement designs that don’t support maximum theoretical bandwidth being used by all available ports and so we don’t need to allocate PCIe lanes <-> USB ports as stringently as your example calculations require.

    Note to other readers (I assume OP already knows): PCIe lane bandwidth doubles/halves when going up/down one generation respectively. So 4x PCIe 4.0 lanes are equivalent in maximum bandwidth to 2x PCIe 5.0 lanes, or 8x PCIe 3.0 lanes.

    edit: clarified what I meant about the 16 “GPU-assigned” lanes.


  • Sure, but not much of that battery improvement is coming from migrating the APU’s process node. Moving from TSMC’s 7nm process to their 6nm process is only an incremental improvement; a “half-node” shrink rather than a full-node shrink like going from their 7nm to their 5nm.

    The biggest battery improvement is (almost definitely) from having a 25% larger battery (40Whr -> 50Whr), with the APU and screen changes providing individually-smaller battery life improvements than that. Hence the APU change improving efficiency “a little”.