Ultimately depends on how the motherboard manufacturers implement it and the choices they provide. If they were smart they wouldn’t narrow lanes, but instead break up most of the higher speed lanes into multiple lower speed ones.

Just as an example, that x16 lane slot to the CPU, with PCIe-6.0 you could break it up into three 4.0x16 slots and four 4.0x4 NVME slots.

Granted, at PCIe-6.0 your probably well beyond the total bandwidth a normal user would need. At that point you hope as the technology matures so it can reduce costs by reducing how many lanes a CPU and motherboard need at all.

For a single device there’s really no benefit right now, but there is a huge benefit for aggregate bandwidth. Your typical consumer motherboard/CPU doesn’t actually have a ton of lanes, most lanes are provided by the PCH, meaning you’re actually sharing bandwidth for a lot of devices. Typically only one x16 slot (for GPU) and an NVME slot are connected directly to the CPU. With PCIe-6.0 and beyond you can break those lanes into more lower speed lanes and not have to share bandwidth.